1. Field of the Invention
The present invention relates to a technique for detecting an error occurring in a process for reading data.
2. Description of the Related Art
A computer system for which high reliability is required allows redundancy in various internal control signals and in data stored in a main storage, enabling quick detection of an error occurrence and correction of the error or the like by taking advantage of the redundancy. In particular, there is a tendency for the frequency of error occurrences in the date stored in the main storage to increase mainly because a large capacity is required for the data, and the data is in many cases protected by an Error Correcting Code (ECC). Using the ECC, it is usually possible to correct one-bit errors and to detect up to two-bit errors.
Such an error detection mechanism is powerless over a control failure in which two pieces of correctly protected (“good ECC”) data are mixed up. That is, the error detection mechanism regards a situation as normal unless there is an error in the content of data, and therefore is not capable of detecting an error even if there is a control failure such as an error in the order of extracting data from a data buffer and referring to the value of a buffer before a new piece of data arrives. These types of errors cannot be detected by the use of hardware in the conventional technique and therefore are revealed merely as errors in the calculation result of a program. These kinds of errors in turn make it extremely difficult to identify the failure cause.